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Rambus Inc. — Download PDF (company IR deck)
Rambus Inc. (RMBS) · 31 slides · Filed Oct 26, 2026
Every slide of this earnings presentation, with the text as published. Open the original deck ↗ · All RMBS deck slides
Slide 1 — Rambus Investor
Rambus Investor Presentation Q3 2026
Slide 2 — Safe Harbor for Forward-Looking Statements; Other Disclosures
This presentation contains forward-looking statements, including those relating to the Company’s expectations regarding business opportunities, the Company’s ability to deliver long-term profitable growth, industry growth rates, timing of expected product launches, demand for existing and newly- acquired technologies, product and investment strategies, the Company’s outlook and financial guidance for recent and upcoming quarters and related drivers, the Company’s ability to effectively manage market challenges, the effects of ASC 606 on reported revenue, and the geopolitical and macroeconomic environment, among other items. Such forward-looking statements are based on current expectations, estimates and projections, management’s beliefs and certain assumptions. Actual results may differ materially. The Company’s business generally is subject to a number of risks which are described more fully in the Company’s periodic reports filed with the Securities and Exchange Commission. The Company undertakes no obligation to update forward-looking statements to reflect events or circumstances after the date hereof. This presentation contains non-GAAP financial measures, including cost of product revenue and operating costs and expenses. In computing these non- GAAP financial measures, stock-based compensation expenses, amortization of acquired intangible assets, facility closure costs, provision for income taxes, and certain other one-time adjustments were considered, if and as applicable. The non-GAAP financial measures should not be considered a substitute for, or superior to, financial measures calculated in accordance with GAAP, and the financial results calculated in accordance with GAAP and reconciliations from these results should be carefully evaluated. Management believes the non-GAAP financial measures are appropriate for both its own assessment of, and to show investors, how the Company’s performance compares to other periods. Reconciliations from GAAP to non-GAAP results are made available and more fully described on our website as well as in the back of this deck and in the earnings release. Safe Harbor for Forward-Looking Statements; Other Disclosures 2
Slide 3 — $2.51
3 Over 3 Decades Technology Leadership San Jose HQ Global Footprint ~800 Employees >70% in Engineering $2.51 Diluted Non-GAAP EPS +25% 5-YR CAGR Product Revenue $348M 2025 Product Revenue Record Revenue $708M 2025 Revenue $360M 2025 Cash from Operations Data Center & AI >75% of Chip and Silicon IP Revenue
Slide 4 — Semiconductor Solutions Built on Innovation
4 Semiconductor Solutions Built on Innovation Automotive Government \ IoT Data Center & Edge Markets Served Chips Memory Interface Chips Security IP Interface IP Silicon IP Rambus Offerings Foundational R&D and IP Innovations Patent Licenses IP Licenses Product Sales
Slide 5 — Amplified Opportunities in Data Center and AI
5 Amplified Opportunities in Data Center and AI Increasing need for performance, delivered securely and reliably Meeting memory performance requirements of growing AI workloads Addressing bandwidth and capacity requirements with novel memory solutions Broadening adoption of key technologies into adjacent markets Server memory hierarchy Increasing bandwidth Increasing latency and capacity HDD Local attach SSD Local attach DRAM Direct attach Cache On chip Novel Memory Multi-rank; serial attach AI Model Sizes (Parameters) Key Technologies: • Memory • Power Management • Clocking • Interconnects • Security Performance Time Time 100B 1T 10T 100T
Slide 6 — Rambus Solutions for the Data Center
6 Rambus Solutions for the Data Center Chips Silicon IP DDR5 RDIMM Server Motherboard AI Accelerator/GPU Card Rambus Products: Memory Interface Chips: Registering Clock Driver, PMIC, SPD Hub, Temperature Sensor Root of Trust Security IP with Quantum Safe Cryptography HBM/GDDR/LPDDR Memory Controller IP + Inline Memory Encryption Security IP PCIe/CXL Controller IP (including Integrity and Data Encryption Security IP) 1 2 3 4 1 4 2 3
Slide 7 — Rambus Memory
Rambus Memory Interface Chips Offering chipset solutions for all industry-standard DDR5 and LPDDR5/5X memory modules Expanding portfolio of new products: • MRCD & MDB 12800 MT/s • PMICs and Voltage Regulators • SPD Hub & Temperature Sensor • Client Clock Driver Industry-leading DDR5 RCDs Gen1 4800 MT/s to Gen6 9600 MT/s DDR5 Server Chipset Complete Chipsets for: • RDIMM • MRDIMM • SOCAMM2 • CUDIMM • CSODIMM • LPCAMM2
Slide 8 — Silicon IP Solutions for AI
Silicon IP Solutions for AI • Critical IP for accelerator, networking and storage chips: HBM, GDDR, LPDDR, PCIe, CXL, PQC, Root of Trust, IME/IDE, MACsec, IPsec and UET-TSS • Key Benefits • Delivers industry-leading bandwidth performance • Enables high-speed connectivity between devices • Protects data at rest, in use and in motion PCIe or CXL Interface IP Security IP IME = Inline Memory Encryption IDE = Integrity & Data Encryption
Slide 9 — Rambus Uniquely Positioned for Novel Memory Solutions
9 Rambus Uniquely Positioned for Novel Memory Solutions Industry leading performance to 12800 MT/s (MRDIMM) and 9600 MT/s (RDIMM) for DDR5-based servers and PCs Industry Leadership World-class expertise in memory interface and interconnect subsystems (digital controller and security IP) Core Expertise Over three decades of research and innovation in high-performance memory, high-speed interfaces, and hardware security Innovation Company founded on mission to drive increased memory bandwidth for greater computing performance Foundation Smart Data Acceleration Engine HBM4E Memory Interface IP DDR5 Memory Interface Chipset RDRAM Synchronous Memory HBM 4 E M e m or y S ubsy st em
Slide 10 — 25%
10 Product Leadership Driving Long-term Growth 2020-2025 25% Product Revenue CAGR* DDR5 & LPDDR5/5X memory module chipsets delivering industry-leading performance Critical interface IP for AI: HBM & GDDR controllers; PCIe controller, switch & retimer Broadest portfolio of secure root of trust, protocol engine, and crypto accelerator cores Experts in interconnect solutions critical for performance and utilization in emerging data center architectures z *Consisting primarily of Memory Interface Chips z
Slide 11 — Financial Highlights
11 Financial Highlights 225 247 348 2023 2024 2025 Product Revenue* ($M) 141 146 167 77 76 82 218 217 249 2023 2024 2025 Pro Forma Operating Expenses ($M) R&D SG&A 196 231 360 1.41 1.68 2.94 0 0.5 1 1.5 2 2.5 3 3.5 0 100 200 300 400 2023 2024 2025 Cash from Operations ($M) & FCF per Share ($) Cash from Ops FCF per Share *Consisting Primarily of Memory Interface Chips 426 482 762 101 113 21 2023 2024 2025 Cash Equivalents & Return of Capital ($M) Cash Equivalents Return of Capital Debt Retirement 7
Slide 12 — Rambus Investment Summary
➢AI-driven data center growth expands long-term market opportunity ➢Broad portfolio of high-performance chips and silicon IP enables critical performance improvements for AI and advanced workloads ➢Innovation feeds sustained product leadership and strong patent portfolio ➢Focused investment advances strategic product roadmap to drive long-term profitable growth ➢Strong cash generation fuels growth initiatives and consistent return of value to stockholders Rambus Investment Summary 12
Slide 13 — Detailed Financials
Detailed Financials Strong cash generation fuels growth initiatives and return of value to stockholders
Slide 14 — Q2 2026 Non-GAAP Income Summary
In Millions, except EPS Q2 2025 Q3 2025 Q4 2025 Q1 2026 Q2 2026 Revenue $172.2 $178.5 $190.2 $180.2 $207.4 Achieved record quarterly revenue Total Operating Costs and Expenses (1) $93.2 $99.3 $103.2 $104.6 $113.7 Continued investment to support core growth initiatives Operating Income (1) $79.0 $79.2 $87.0 $75.6 $93.7 Profitable results drive cash generation Diluted Earnings Per Share (1) $0.62 $0.62 $0.68 $0.63 $0.77 EPS grows 21% sequentially and 24% YoY (1) Please refer to reconciliations of non-GAAP financial measures included in this presentation and in our earnings release Q2 2026 Non-GAAP Income Summary 14
Slide 15 — Q2 2026 Balance Sheet Summary
Q2 2026 Balance Sheet Summary In Millions Q2 2025 Q3 2025 Q4 2025 Q1 2026 Q2 2026 Total Cash & Marketable Securities $594.8 $673.3 $761.8 $786.1 $824.9 Driven by consistent cash from operations Total Assets $1,467.8 $1,406.4 $1,529.5 $1,533.1 $1,612.3 Strong balance sheet and debt free Stockholders’ Equity $1,228.0 $1,288.5 $1,364.4 $1,393.2 $1,466.7 Cash from Operations $94.4 $88.4 $99.8 $83.2 $61.2 Solid cash generation 15
Slide 16 — Reconciliation of GAAP to Non-GAAP Financial Measures
Operating Income in Millions, except EPS Q2 2025 Q3 2025 Q4 2025 Q1 2026 Q2 2026 GAAP Operating Income $63 $63 $71 $62 $73 Adjustments: Stock-based compensation 14 14 14 11 16 Amortization of acquired intangible assets 2 2 2 2 2 Restructuring and other charges 0 0 0 1 3 Non-GAAP Operating Income $79 $79 $87 $76 $94 Net Income in Millions, except EPS Q2 2025 Q3 2025 Q4 2025 Q1 2026 Q2 2026 GAAP Net Income $58 $48 $64 $60 $68 Adjustments: Stock-based compensation 14 14 14 11 16 Amortization of acquired intangible assets 2 2 2 2 2 Restructuring and other charges 0 0 0 1 3 Provision for income taxes (7) 4 (5) (4) (4) Non-GAAP Net Income $67 $68 $75 $69 $84 Diluted Earnings Per Share $0.62 $0.62 $0.68 $0.63 $0.77 Reconciliation of GAAP to Non-GAAP Financial Measures *Certain amounts may be off $1M due to rounding. 16
Slide 17 — Reconciliation of GAAP to Non-GAAP Income Statement
Reconciliation of GAAP to Non-GAAP Income Statement GAAP Non-GAAP Delta In Millions, except EPS Actual Actual to Q2 2026 Q2 2026 GAAP Revenue $207.4 $207.4 $- Cost of revenue 42.0 40.2 (1.8) Research and development 51.1 45.0 (6.1) Sales, general and administrative 38.3 28.5 (9.7) Restructuring charges 3.3 0.0 (3.3) Total operating cost and expenses 134.7 113.7 (20.9) Operating income 72.7 93.7 20.9 Interest and other income (expense), net 6.8 6.8 0.0 Income before income taxes 79.5 100.4 20.9 Provision for income taxes (1) 11.9 16.1 4.2 Net income $67.6 $84.4 $16.7 Diluted EPS $0.61 $0.77 $0.16 * Certain amounts may be off $0.1M due to rounding. (1) Assumes a non-GAAP tax rate of 16%. 17
Slide 18 — Revenue and Licensing Billings
Revenue and Licensing Billings ¹ Licensing billings is an operational metric that reflects amounts invoiced to our patent and technology licensing customers during the period, as adjusted for certain differences relating to advanced payments for variable licensing agreements. 2 Interest income associated with the significant financing component of licensing agreements as a result of the adoption of ASC 606. * Certain amounts may be off $0.1M due to rounding. ASC 606 ASC 606 In Millions Q1 2025 Q2 2025 Q3 2025 Q4 2025 FY 2025 Q1 2026 Q2 2026 YTD 2026 Product Revenue $76.3 $81.3 $93.3 $96.8 $347.8 $88.0 $99.2 $187.2 Royalties Revenue 74.0 68.6 65.1 71.7 279.4 69.6 84.2 153.9 Contract and Other Revenue 16.4 22.3 20.1 21.8 80.5 22.6 24.0 46.5 Total $166.7 $172.2 $178.5 $190.2 $707.6 $180.2 $207.4 $387.6 In Millions Q1 2025 Q2 2025 Q3 2025 Q4 2025 FY 2025 Q1 2026 Q2 2026 YTD 2026 Royalties Revenue $74.0 $68.6 $65.1 $71.7 $279.4 $69.6 $84.2 $153.9 Licensing Billings (1) 73.3 66.4 66.1 71.5 277.2 70.8 84.1 154.8 Delta ($0.7) ($2.2) $1.0 ($0.2) ($2.2) $1.2 ($0.2) $0.9 In Millions Q1 2025 Q2 2025 Q3 2025 Q4 2025 FY 2025 Q1 2026 Q2 2026 YTD 2026 ASC 606 Interest Income (2) $0.1 $0.0 $0.2 $0.0 $0.3 $0.1 $0.0 $0.1 18
Slide 19 — Product Overview
Product Overview Industry-leading Chips and Silicon IP
Slide 20 — Chips
20 Chips Providing memory bandwidth, capacity, and power efficiency to unleash the performance of CPUs and accelerators Chips Silicon IP Innovations Server Module Chipsets • DDR5 RDIMM • DDR5 MRDIMM • LPDDR5X SOCAMM2 Client Module Chipsets • DDR5 CU/CSODIMM • LPDDR5 LPCAMM2
Slide 21 — DDR5 RDIMM Chipset
21 Industry-leading Performance and Margin • Compliant with latest JEDEC spec up to 9600 MT/s • Wide margin IO design with advanced programmability • Exceeds JEDEC reliability requirements Optimized Power • Frequency-based power optimization Best-in-class Debug and Serviceability • Integrated tools for bring-up and debug • Works out of the box with default system BIOS Use Cases • Server RDIMM 9600, 8000, 7200, 6400, 5600, 4800 (RCD, PMIC, SPD Hub, Temp. Sensors x2) DDR5 RDIMM Chipset DDR5 RDIMMs with Rambus Registering Clock Driver, PMIC, SPD Hub and Temperature Sensor ICs
Slide 22 — DDR5 MRDIMM 12800 Chipset
22 DDR5 MRDIMM 12800 Chipset Leading Performance • Supports industry-standard MRDIMM 12800 • Full chipset solution • Advanced clocking, control and power management • Supports standard and tall (high capacity) form factors • Common architecture with RDIMM 8000+ to allow flexibility and scalability in server memory configuration • Best-in-class reliability and serviceability Use Case • Server MRDIMM 12800 (MRCD, MDB x10, PMIC, SPD Hub, Temp. Sensors x2) DDR5 MRDIMM 12800 with Rambus Memory Interface chips: Multiplexed Registering Clock Driver, Multiplexed Data Buffer, PMIC, SPD Hub and Temperature Sensor ICs
Slide 23 — LPDDR5X SOCAMM2 Server Module Chipset
23 • First in a planned family of LPDDR-based server module chipsets for future AI systems • Full chipset for JEDEC-standard LPDDR5X SOCAMM2 • Supports data rates up to 9.6 Gb/s • Provides module configuration, telemetry, and localized, efficient power conversion • Enables AI data center performance scaling in a low-power, high-bandwidth, compact form factor LPDDR5X SOCAMM2 Server Module Chipset LPDDR5X SOCAMM2 Server Module with Rambus 12A and 3A Voltage Regulators and SPD Hub
Slide 24 — LPCAMM2 Memory Module Chipset
24 • Supports wide range of PC performance and capacity use cases • Supports data rates to 10666 MT/s • I2C and I3C Basic bus serial interface • Excellent power conversion efficiency • Programmability features for customization LPCAMM2 Memory Module Chipset LPCAMM2 Module with PMIC5200 and SPD Hub
Slide 25 — DDR5 CSODIMM/CUDIMM Chipsets
25 • Support wide range of PC performance and capacity use cases • Support data rates to 9600 MT/s • I2C and I3C Basic bus serial interface • Excellent power conversion efficiency • Programmability features for customization DDR5 CSODIMM/CUDIMM Chipsets DDR5 CSODIMM with Client Clock Driver, PMIC5120 and SPD Hub
Slide 26 — Silicon IP
Silicon IP Enabling accelerated computing with high-performance interfaces and hardware-level security Chips Silicon IP Innovations Interface IP • HBM • GDDR • LPDDR • PCI Express • CXL Security IP • Root of Trust • MACsec • IPsec • UET-TSS • IME
Slide 27 — Interface IP: Memory Interface and Interconnect IP
27 Interface IP: Memory Interface and Interconnect IP Memory Controllers Interconnect Controllers Video Compression DDR LPDDR GDDR HBM CXL PCI Express MIPI VESA FEC Application Focus 4 4X/5X/5T 6/7 2/2E 3/3E 4/4E 2.0 3.1 6.3 7.0 CSI-2/ DSI-2 DSC/ VDC-M DP/ HDMI Data Center AI/Edge Automotive Government & Defense IoT Availability Now Now Now Now Now Now Now Now Now Now Now Now Now ISO 26262 (Automotive)
Slide 28 — Security IP: Protecting Data at Rest, in Motion, and in Use
28 Security IP: Protecting Data at Rest, in Motion, and in Use Root of Trust Network Security Cipher Engines Crypto Cores Provisioning Application Focus Programmable Firmware Controlled MACsec UET-TSS IPsec TLS IME Crypto TRNG Infrastructure Key Management Data Center AI/Edge Automotive Government & Defense IoT Availability Now Now Now Now Now Now Now Now Now Now FIPS 140 CMVP, NIST (Government) ISO 26262 Common Criteria Quantum Safe N/A N/A N/A N/A N/A SESIP/PSA N/A N/A N/A
Slide 29 — Rambus Labs
Rambus Labs Enabling next-generation data centers through innovation, research and development Chips Silicon IP Innovations Next-Gen Memory Post-Quantum Computing Security
Slide 30 — Key Areas of Focus for Rambus Labs
30 Key Areas of Focus for Rambus Labs Next-Gen Memory Architectures and Performance Secure and Reliable Memory Systems Security for AI/ML and Post-Quantum Computing Strategic Customer & Product Roadmap Support
Slide 31 — Thank you
Thank you